Talk:Zero instruction set computer Source: en.wikipedia.org/wiki/Talk:Zero_instruction_set_computer

Attribution

A lot of the text on this page is directly cribbed from the first link http://www.lsmarketing.com/LSMFiles/9809-ai1.htm

The link is given, but the text is not attributed. It should be rewritten. Heck, it should be rewritten anyways; it's barely intelligible. Dyfrgi 18:07, 14 September 2006 (UTC)[reply]

I would be very grateful to the one, who changed the names of the ZISC contributors, to respect the truth. The Wikipedia Foundation has enough trouble today with the "experts issue" to add any. There is no place here for personal ego issues. The ZISC implementation, as far as micro electronics is concerned, has been invented by Dr. Tannhof, and this creation has been patented by him at IBM under his name. The fact that someone else helped Dr Tannhof in his work is not a valid reason to change the ZISC entry in here. Thank you. Didier_Morandi 13:46, 2 December 2007 (UTC)[reply]

The IBM patent lists the first person to apply for a patent and who one. If an inventor is international or doesn't believe their invention has any value (as would be the case if they simply wrote a theoretical treatise and did not ever plan on having it implemented), then the first patent holder would not be the inventor. There are papers as early as 1989 published in france describing the architecture of neural networking chips, per ieee, and the current source cited makes no claims of invention. As such, I don't believe there are any reliable sources for who invented the ZISC architecture, at this time. Eaterjolly (talk) 04:15, 1 January 2017 (UTC)[reply]

Here's an earlier paper I found. That paper also cites the following in it's references from a 1986 paper "D. E. Rumelhart, J. L. McClelland, Parallel Distributed Processing (PDP): Exploration in the Microstructure of Cognition, vol. 1, 1986, MIT Press." So Rumelhart would be the closest thing to an inventor we have, not that we have a source to confirm that for us. Eaterjolly (talk) 05:00, 1 January 2017 (UTC)[reply]

Transport triggered architecture

Isn't this just a transport triggered architecture with the only operation being a compare? Sounds like someone's coining fancy names and patenting just a specific implementation of a TTA. .froth. (talk) 18:42, 18 June 2008 (UTC)[reply]

As far as I can tell, the architecture that Kevin Dowd in 1989 called a ""ZISC" Zero Instruction Set Computer Architecture" is identical to a transport triggered architecture.

However, the architecture currently described in this Zero Instruction Set Computer article sounds more like a content-addressable memory.

How is this kind of ZISC different from a content-addressable memory ? --68.0.124.33 (talk) 13:29, 20 October 2008 (UTC)[reply]

I worked, though only a few days, on a ZISC chip mounted on a PC board, lent by the IBM Corbeil-Essonnes lab to the IBM ECAM (European Center of Applied Mathematics) in Paris, France, around 1995. I see absolutely no relationship between it and a content addressable memory. I would rather see it as an hardware implementation of a environment designed to host a Kohonen network. It was pretty good at making a classifying job, and you could for instance "teach" him to drive a simulated car on a smilated circuit (on the PC screen) in a matter of minutes, on the basis of : "If the pattern you see is this, do that; if you do not know, ask and incorporate it in your pattern => action set; if not answered, compare it to the patterns you now, determine the distance of each and make a reasonable guess; if corrected, memorize the corrected action, and so on.

The chip was efficient. Unfortunately, while we were doing a lot of classifying jobs for data mining and text mining, the department manager was not convinced we could immediately afford to change our methods and abandon all of our existing algorithms. The neuron network specialist of the department, Jean Fargues, also disappeared a few months later in tragic circumstances and so we never put the ZISC in production work. 82.226.27.88 (talk) 14:34, 18 February 2013 (UTC)[reply]

External links modified

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Potentially Useful Sources

http://scholar.googleusercontent.com/scholar?q=cache:eioYQ1GtXLoJ:scholar.google.com/+zisc&hl=en&as_sdt=0,36&as_yhi=1994 Royal Institute of Technology | Department of Physics - Frescati, Stockholm, Sweden Eaterjolly (talk) 01:45, 1 January 2017 (UTC)[reply]

Proposed addition

In September 2014, an open-source accelerator card based on an array of CM1K chips connected to an FPGA, was demonstrated and used to accelerate the calculation of large arrays of linear regressions. In particular, the generation of high-resolution brain connectivity maps was demonstrated using Resting state fMRI time-series, the correlation between which was approximated through a measure based on the L1-norm.^[1] ( Lminati (talk) 15:24, 12 March 2019 (UTC) )[reply]

This would need a secondary source. - MrOllie (talk) 21:45, 25 June 2019 (UTC)[reply]

Stub-class plus problems

Just about everything in this article that extends the article past stub class is problematic. I couldn't find a clear enough sentence or paragraph to bother copying into my own notes. And I don't feel like I comprehended anything, either.

I'm trying to be realistic in my assessment here, but it's hard to see anything here that isn't an RfD in slow motion. Mine is just one opinion, but as I see it, this article really needs to become more clear in some tangible way to justify its continued existence. — MaxEnt 04:59, 12 June 2020 (UTC)[reply]

^ ^a ^b Minati L, Zacà D, DIncerti L, Jovicich J "Fast computation of voxel-level brain connectivity maps from resting-state functional MRI using l1-norm as approximation of Pearson's temporal correlation: Proof-of-concept and example vector hardware implementation"

[minati-1] Minati L, Zacà D, DIncerti L, Jovicich J "Fast computation of voxel-level brain connectivity maps from resting-state functional MRI using l1-norm as approximation of Pearson's temporal correlation: Proof-of-concept and example vector hardware implementation"

[1]